DRF100 15v, 8a, 30mhz the DRF100 is a high-speed power mosfet driver with a unique anti-ring function. it is intended to drive the gate of a power mosfet with 3nf gate capacitance to 15v at frequencies up to 30mhz. it can produce output currents 8a rms, while dissipating 60w. the driver output can be configured as inverting or non-inverting. typical applications ? mosfet drivers ? switch mode power ampli ers ? digital output ampli ers ? pulse generators ? laser diode drivers ? ultrasound transducer drivers ? acoustic optical modulators features ? switching frequency: dc to 30mhz ? low pulse width distortion ? single power supply ? 1v cmos schmitt trigger input 1v hysteresis ? inverting non-inverting select ? rohs compliant ? output capable of 8a rms ? power dissipation capability 60w symbol parameter ratings unit v dd supply voltage 18 v in, fn input single voltages -.7 to +5.5 i o pk output current peak 8a t jmax operating temperature 175 c mosfet driver hybrid driver absolute maximum ratings driver speci cations symbol parameter min typ max unit v dd supply voltage 81518 v in input voltage 3 5.5 in (r) input voltage rising edge 3 ns in (f) input voltage falling edge 3 i ddq quiescent current 2ma i o output current 8a c oss output capacitance 2500 pf c iss input capacitance 3 r in input parallel resistance 1m v t(on) input, low to high out 2.0 2.8 v v t(off) input, high to low out 1.0 1.4 t dly time delay (throughput) 25 38 ns t r rise time 1.5 2.5 3.0 ns t f fall time 1.5 2.5 3.0 t d prop. delay 35 microsemi website - http://www.microsemi.com 050-4912 rev d 4-2009 DRF100
DRF100 output characteristics symbol parameter min typ max unit c out output capacitance 2500 pf r out output resistance 1 l out output inductance 2 3 4 nh f max operating frequency cl=3000nf + 50 30 mhz f max operating frequency rl=50 50 dynamic characteristics symbol parameter min typ max unit c iss input capacitance 2000 pf c oss output capacitance 165 c rss reverse transfer capacitance 75 thermal characteristics symbol parameter ratings unit r jc thermal resistance junction to case 1.44 c/w r jhs thermal resistance junction to heat sink 2.53 t jstg storage temperature -55 to 150 c p d maximum power dissipation @ t sink = 25c 60 w p dc total power dissipation @ t c = 25c 100 microsemi reserves the right to change, without notice, the speci cations and information contained herein. 050-4912 rev d 4-2009 figure 1, DRF100 simpli ed circuit diagram the simpli ed DRF100 circuit diagram is illustrated above. by including the driver high speed by-pass capacitor (c internal), the contri bution to the internal parasitic loop inductance of the driver output is greatly reduced. this low parasitic approach, coupled with t he schmitt trig- ger input (pin 4), kelvin signal ground (pin 5) and the anti-ring function, provide improved stability and control. the in pin (4) is applied to a schmitt trigger. the signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed speci cally for ring abatement. the p channel and n channel power drivers provide the high current to the output (pin 9.)
the function (fn, pin 3) is the invert or non-invert select pin, it is internally held high, normally non-inverting. microsemi?s products are covered by one or more of u.s. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,5 03,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743 and foreign patents. us and foreign patents pending. all rights res erved. DRF100 050-4912 rev d 4-2009 the test circuit illustrated above was used to evaluate the DRF100 (available as an evaluation board DRF100 / evalsw.) the inp ut control signal is applied to the DRF100 via in(4) and sg(5) pins using rg188. this provides excellent noise immunity and control of th e signal ground currents. the +v dd inputs (2,6) are by-passed (c1, c2, c4-c9), this is in addition to the internal by-passing mentioned previously. the capacito rs used for this function must be capable of supporting the rms currents and frequency of the gate load. figure 2, DRF100 test circuit truth table *referenced to sg fn (pin 3)* in (pin 4)* function output high high non-invert high high low non-invert low low high inverting low low low inverting high
figure 3, DRF100 mechanical outline all dimensions are .005 DRF100 050-4912 rev d 4-2009 pin assignments pin 1 ground pin 2 u1 +vdd pin 3 fn pin 4 u1 in pin 5 u1 sg pin 6 u1 +vdd pin 7 ground pin 8 source pin 9 drain pin 10 source r0.150 4plcs ?0.125 4plcs 0.320 0.250 0.250 1.500 0.275 0.200 0.200 0.370 0.275 0.300 0.040 0.570 0.300 0.275 large leads - 0.200", 2 plcs gaps - 0.090" , 2 plcs 0.125 0.125 medium leads - 0.065", 2 plcs small leads - 0.040", 3 plcs gaps - 0.050", 6 plcs 1 23 45 6 7 10 9 8 .005" typ. half hard copper gold plated drf 1 0 0
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